FIG. 1 illustrates a conventional four transistor (4T) imager pixel 100 coupled via column line 125 to a conventional pixel reading circuit 150. The pixel 100 includes a light sensitive element 101, reset, source follower, row select, and transfer transistors 110-114, and nodes A, B, E, and P. Control signals RESET, TX, and ROW are respectively applied to the gates of the reset transistor 110, the transfer transistor 114, and the row select transistor 112. Node A is connected to a supply voltage source (VAAPIX) for the pixel 100. Node E is a floating diffusion, i.e., a charge storage node. Node P is a charge accumulation node of the light sensitive element 101. The outputs produced by the pixel 100 are made available at node B. These outputs include a reset output voltage Vrst present at node B after the resetting of node E by reset transistor 110 and a pixel image signal output voltage Vsig present at node B after the transfer of charge accumulated in the light sensitive element to node E by the transfer transistor 114.
The pixel reading circuit 150 includes a reset signal sample and hold (SH) circuit 151 for sampling and holding the reset signal Vrst. The pixel reading circuit 150 also includes a photo signal sample and hold circuit 152 for sampling and holding the photo signal Vsig. The sample and hold circuits 151, 152 are respectively triggered when control signals SHR, SHS are asserted to sample and hold the reset Vrst and photo Vsig signals. The pixel reading circuit further includes a differential amplifier 160, a bias circuit 170, and nodes C and D. As illustrated, column line 125 couples the output of the pixel at node B to the input of the pixel reading circuit at node C. The output of the differential amplifier 160 is presented at node D.
The pixel 100 is operated by asserting the ROW control signal to cause the row select transistor 112 to conduct. The RESET control signal is asserted to cause a reset voltage from node A (e.g., VAAPIX) to be applied to charge storage node E to cause the pixel 100 to output a reset signal Vrst through transistors 111 and 112. The SHR control signal is asserted to cause the sample and hold circuit 151 to sample and hold the reset signal Vrst. The RESET and SHR control signals are then deasserted. The light sensitive element 101 is exposed to light during a charge integration period, i.e., an exposure period. During the exposure, the light sensitive element 101 produces and stores charge related to the amount of incident light. Charge accumulates at node P based on the intensity of the incident light and the length of the integration period. At the end of the integration period, the accumulated charge is transferred to storage node E by transistor 114 by asserting the TX control signal to cause the pixel 100 to output a photo signal Vsig through transistors 111 and 112. The SHS control signal is asserted to cause the sample and hold circuit 152 to sample and hold the photo signal Vsig. The TX and SHS control signals are then deasserted. Both the reset signal Vrst and the photo signal Vsig are output at node B, albeit at different times. The bias circuit 170 biases the column line 125 to provide a stable signal path for the reset and photo signals Vrst, Vsig.
As noted, the reset signal Vrst is sampled and held by the reset signal circuit 151, while the photo signal Vsig is sampled and held by circuit 152. The sampled and held photo and reset signals are supplied as inputs to differential amplifier 160, which generates the pixel output signal Vpixel=(Vrst−Vsig). As the reset Vrst and photo Vsig signals are produced during the same image frame, this is known as correlated double sampling (CDS) which minimizes the effect of kTC noise associated with the pixel 100 and the pixel reading circuit 150. The resulting pixel output signal Vpixel is output at node D.
FIG. 2 is a block diagram of an imager 200 having a pixel array 201. Pixel array 201 comprises a plurality of pixels 100 arranged in a predetermined number of columns and rows.
Typically, the imager 200 is operated on a rolling shutter basis, in which the rows of pixels are sequentially selected for read out, where each pixel in a selected row outputs its reset Vrst and photo Vsig signals at the same time to a corresponding set of pixel reading circuits. That is, a row of pixels from the array 201 is selected by the control circuit 250 by sending a row address from the control circuit 250 to the row decoder 220. The row decoder 220 decodes the row address and operates the row driver 210. The row driver 210 asserts the ROW control signal on a line coupled to the row select transistor 112 of each pixel in the selected row.
The assertion of the ROW control signal causes the row select transistor 112 of each pixel 100 in the selected row to conduct. The column driver 260 includes the same number of pixel reading circuit 150 as the number of pixels 100 in each row of the pixel array 201, so that each pixel in a selected row is associated with its own pixel reading circuit 150. This permits each pixel 100 in the selected row to output its reset Vrst and photo Vsig signals at node B, which is received at node C of the associated pixel reading circuit 150. Each pixel reading circuit 150 outputs a corresponding pixel output signal Vpixel at node D. The control circuit 250 operates the column decoder 260 to cause the column driver circuit 270 to select a column from the selected pixels. The output from node D of the pixel reading circuit 150 associated with the pixel in the selected column is routed via node D′ to an analog to digital converter 280, which converts the output to a digital value.
The analog to digital converter 280 is coupled to an imager processor 290. The image processor operates upon the digital values produced by the analog to digital converter 280 and outputs a processed digital value to the output circuit 295. If the imager 200 is a color imager, it is important that the digital values pixel output signals Vpixel, and thus the corresponding digital values produced by the analog to digitail converter 280, are linear functions of the incident light. The output circuit 295 is used to send the processed digital value to other devices (not illustrated). The other devices may be, for example, an internal storage device, a removable memory device, a display screen, or an external interface.
It is desirable for an imager 200 to be capable of imaging in the presence of a high level of dynamic range in the brightness of the light incident upon the pixels 100. It is desirable for the imaging to be performed as a linear function of incident light. However, for any given integration period, in the presence of incident light having a high level of brightness, there is a danger of overexposure due to the light sensitive element 101 producing too many photo generated charges. Conversely, in the presence of incident light having a low level of brightness, there is a danger of underexposure due to the light sensitive element 101 producing too few photo generated charges. Accordingly, there is a need and desire for an imager capable of linearly operating over a high dynamic range.